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NCL30001
CT
Adj.
Jitter
Jitter
FB
+
FB overload
comparator
+
?
V OVLD
Overload
Timer
t OVLD
Enable
S
Q
R
OVLD
FFBrown ? Out
V BO
Reset
Oscillator
DC Max
Sawtooth
Ramp. Comp.
Clock
DC Max
Ramp Comp
V FF
+
V
Comparator
?
+
BO
Out x2
Enable
counter
Dual HV
start ? up
current source
Startup
Adj.
V CC(off) HV current
CCOK
Ramp
Comp
+
AC In skip
comparator
V
Reset
Reset
Start
V CC
Management
V DD
GND
V DD
+
?
V SSKIP(sync)
V DD
Clock
Soft ? skip Ramp
FB
R
+
FB skip
Comparator
+
?
Delay
t SSKIP
Start
Terminate
DC Max
V SSKIP
+
AC IN
FB
FB
+
Transient Load Detect
Comparator
?
Ramp Comp
V SSKIP(TLD)
V ? to ? I
V ? to ? I
21.33k W
+
?
PWM Skip
Comparator
S
Q
R
Output
Driver
DRV
V FF
Reference
Generator
V FF
+
?
gm
AC error
Amplifier
V ? to ? I
+ inverter
21.33k W
+
?
PWM
comparator
+
V CC
CM
4V
OVLD
Latch
BO
V CC OK
Blanking
t LEB
gm
I spos
AC COMP
V DD
OVP Comparator
Current sense
amplifier
+
I avg
+
?
Latch ? Off
I latch(clamp)
V latch(high)
OTP Comparator
blanking
t Latch (delay)
I latch(shdn)
+
?
+
S
Q
R
Latch
TEST
V latch(clamp)
V latch(low)
Reset
Figure 1. Detailed Block Diagram
http://onsemi.com
2
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